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Associate Manager-TA at SiSoC Semiconductor Technologies Pvt Ltd. Β· SiSoC Semiconductor
10d ago

Senior Lead Memory Design EngineerSiSoC Semiconductor

πŸ“ Location: Bengaluru, India 🏒 Domain: VLSI | Semiconductor | Non-Volatile Memory (NVM) IP Design πŸ’Ό Experience: 7Years to 9Years About the Role: We are looking for an experienced Senior Lead Engineer – Memory Design to join a global Non-Volatile Memory (NVM) IP design team in Bengaluru. This role involves leading NVM IP benchmarking, onboarding, release, automation, and technical support across third-party and proprietary NVM IP platforms. You will collaborate with global engineering teams, technology partners, silicon foundries, and product design teams to deliver high-quality, scalable IP solutions. Key Responsibilities: Lead NVM IP benchmarking based on product and technology requirements. Manage IP onboarding, design kit preparation, verification, and release to product teams. Support NVM IP integration, debugging, and troubleshooting. Develop and maintain automated IP onboarding and release flows. Manage third-party and proprietary NVM IP portfolios across technology nodes ranging from 180nm to 5nm. Work with NVM technologies, including Logic-NVM, Flash, RRAM, and MRAM. Collaborate with vendors, silicon foundries, and global engineering teams across India, Europe, and the US. Drive the complete NVM IP development lifecycle, ensuring quality and timely delivery. Coordinate with digital design, reliability, and test engineering teams. Track project progress, communicate updates to stakeholders, and mentor junior engineers. Required Qualifications: Bachelor's or Master's degree in Electronics or Electrical Engineering. 7Years to 9Years of experience in Analog Design, Memory Design (SRAM/NVM), or Foundation IP Design (I/O/Standard Cells). Hands-on experience in scripting and design-flow automation. Experience working with cross-functional engineering teams throughout the design lifecycle. Knowledge of quality-managed design flows, methodologies, and EDA tools such as Cadence and Synopsys. Strong communication, stakeholder management, and collaboration skills. Good to have: Knowledge of NVM technologies, memory macro architecture, and IP design methodologies. Experience working with third-party IP vendors and semiconductor foundries.Exposure to advanced technology nodes and IP integration processes. πŸ“© Interested candidates? Please share your updated profile at Bhagyalakshmi.m@sisocsemi.com or refer suitable professionals from your network. Let's connect and explore exciting opportunities in the semiconductor industry!#Hiring #SiSoCSemiconductor #VLSI #Semiconductor #MemoryDesign #NVM #IPDesign #AnalogDesign #SRAM #FlashMemory #RRAM #MRAM #BengaluruJobs
tal sayslead nvm ip benchmarking, onboarding, and release for global memory design products in bangalore
engineering lead Bangalore cadencesynopsys
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comments 2 anon

anon #253602 19 Oct 2026
Thanks a lot for sharing
anon #66e93d 19 Oct 2026
how will we know if we are shortlisted
you'll show as anon #xxxxxx. be kind.
Senior Lead Memory Design Engineer Bhagyalakshmi M Β· SiSoC Semiconductor
message boss β†—