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Chip design AI Infrastructure recruiter @AsteraLabs / Hiring: PCIe/ CXL/ Ethernet/ SerDes experts / Ex - Qualcomm, Cypress, Salesforce / @20 Years in recruiting! · Astera Labs
13d ago

RTL Design EngineerAstera Labs

Astera Labs Bangalore is hiring! RTL design engineers with 5+ years of experience for our IP /SOC design engineering teams with PCIe/ Ethernet/ CXL/ Networking Interconnects / NOCs / Switch / Chiplet / PIPE/ UCIe expertise. DM or email me for details. #RTL #RTLDesign #IPDesign #SOCDesign #PCIe #UCIe #CXL #Ethernet #NOCs #Switch #PIPE #Chiplet #CustomASIC #Switch #IPDesign #Hiring #DesignHiring #Bangalore #AIinfra #AIinfrastructure #AsteraLabs
tal saysastera labs in bangalore is hiring rtl design engineers with 5+ years of experience
engineering senior Bangalore public rtlpciecxlethernetsoc
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RTL Design Engineer Jayant Joshi · Astera Labs
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