Hiring for the next generation purpose built AI Infra - PCIe, Ethernet, Switches, CXL| @Astera Labs | Ex - Qualcomm, Cypress, Salesforce
3d ago
Staff Engineer, Static Timing Analysis@Astera Labs
Astera Labs, Bangalore. I am hiring at 10+ years of hands-on experience in Static Timing Analysis on complex. ASIC/SoC designs, Proven track record of full-chip top-level STA signo
Astera Labs, Bangalore. I am hiring at 10+ years of hands-on experience in Static Timing Analysis on complex. ASIC/SoC designs, Proven track record of full-chip top-level STA signoff on at least one tapeout at advanced nodes (7nm or below), Deep expertise with PrimeTime, PrimeTime SI, and SDC constraint development, Experience with high-speed connectivity SoCs (PCIe Gen 6/7, CXL, UALink, or Ethernet), ETM/ILM models. DM me or jayant.c@asteralabs.com for more details!
#Astera #AIconnnectivity, #PCIe #CXL #UAlink #Ethernet #STA #Timing #Primetime #PrimetimeSI #SOCs #ASICs #VLSI #AI #Connectivity #AIinfra #datacenter #NICs #Bangalore
tal sayshiring a staff engineer with 10+ years of experience in static timing analysis for asic/soc designs.
engineering
staff
Bangalore
primetimesdcpciecxlethernet
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