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🚀 **Hiring: Design Verification (DV) Engineers | 3–4 Years of Experience** Garudaven Private Limited We are looking for skilled Design Verification Engineers with hands-on experience in IP and SoC verification. **🔹 Required Skill Set** - Hands-on experience with **UVM-based verification** - Good understanding of Verilog and digital design fundamentals - Experience developing and debugging constrained-random testbenches - Knowledge of assertions (SVA), functional coverage, and code coverage - Good understanding of test planning, testbench architecture, and coverage closure - Experience with simulation and debugging tools such as VCS, QuestaSim, or Xcelium - Proficiency in waveform analysis and debugging simulation failures - Familiarity with regression testing and scripting using Python, Perl, or shell is an added advantage **🔹 Preferred Experience** - IP-level or soc level verification - Protocol verification such as AMBA APB, AHB, AXI, SPI, I2C, UART, PCIe, or Ethernet **🔹 Experience:** 3–4 Years **🔹 Domain:** VLSI / Semiconductor Design Verification **🔹 Location:** Bangalore (WFO) **🔹 Notice Period:** Immediate Joiners 📩 Interested candidates can share their updated resumes to bhargavi.t@garudaven.com or DM or comment below. Please share this post with suitable candidates in your network! #VLSI #DesignVerification #SystemVerilog #UVM #Semiconductor #ASICVerification #Hiring